The present invention relates to a ferroelectric memory device.
As a ferroelectric memory device, an active ferroelectric memory device including 1T/1C cells in which one transistor and one ferroelectric capacitor are disposed in each memory cell, or including 2T/2C cells in which a reference cell is further disposed in each memory cell, has been known. As a nonvolatile memory device which is more suitable for an increase in capacity, a ferroelectric memory device in which each memory cell is formed by one ferroelectric capacitor has been proposed (Japanese Patent Application Laid-open No. 9-116107).
In a conventional ferroelectric memory device, data is read by detecting the change in the amount of charge which occurs when applying a read voltage to the ferroelectric capacitor. This method of reading data is easily influenced by variation of characteristics of the ferroelectric capacitor in each memory cell, since a read margin is comparatively small.